1. Field of the Invention
The present invention relates to a timing controller and a delay circuit (controlled delay circuit), and more particularly, to a timing controller adopted for electronic circuits, for controlling the timing of a signal by changing the phase of the signal.
2. Description of the Related Art
Recent computers employ high-speed CPUs (central processing units: MPUS) and electronic circuits. These high-speed devices require high-speed interfaces.
The access time of a synchronous memory (for example, synchronous dynamic random access memory: SDRAM) is basically determined by a delay time in an input buffer, a delay time in long wiring, and a delay time in an output buffer. These delay times are reducible only by reducing the chip size or by improving the transistor characteristics. It is very difficult, therefore, to provide high-speed synchronous memories.
LSI chips are becoming larger, and the delay time in the long wiring reaches one nanosecond or more. These are many LSIs that have an access time of five nanoseconds or longer. The long access time limits the rate of continuous access operations to about 100 MHz.
On the other hand, the signal frequency inside a chip can be increased by employing a pipeline structure and parallel-serial conversion. An output circuit of the chip, however, is incapable of following the internal speed of the chip. It is required, therefore, to provide a timing controller for properly controlling the timing of a control signal to the output circuit according to the period of the control signal. The problems of the prior art will be explained hereinafter in detail with reference to the accompanying drawings.
An object of the present invention is to provide a timing controller for properly controlling the timing of a control signal according to the period of the control signal. Further, another object of the present invention is to provide a controlled delay circuit for obtaining a signal including a required delay time or a required frequency by decreasing consumption power without receiving influence of noises caused by power voltage or temperature fluctuations. In addition, still another object of the present invention is to provide a controlled delay circuit (control signal generator) capable of correctly generating a high-speed clock signal without a quantization error or an offset, as well as providing a controlled. delay circuit used for such a control signal generator.
According to the present invention, there is provided a controlled delay circuit comprising a first gate chain for measuring a time difference between a changeover point of a first control signal and a changeover point of a second control signal; and a second gate chain, receiving third signals which are generated in the first gate chain and represent the time difference, for providing an appropriate delay time from an input to an output depending on the time difference.
The third control signal may be stored in a memory or a register circuit to fix the third control signal. The data stored in the memory or register circuit may be renewed in accordance with specific clock cycles.
Further, according to the present invention, there is provided a controlled delay circuit comprising a first gate chain having gate circuits connected in series to transmit a signal in a first direction; a second gate chain having gate circuits connected in series to transmit a signal in a second direction opposite to the first direction; and a control circuit for activating and inactivating at least a part of the first gate chain according to a first control signal and at least a part of the second gate chain according to a second control signal, and at least one node in the first gate chain being short-circuited to at least one node in the second gate chain, to invert an input signal to the first gate chain and provide an output signal from the second gate chain.
A number of the gate circuits in the first gate chain may be at least three and be equal to or greater than a number of the gate circuits in the second gate chain. The first and second control signals may be produced according to a common signal, which may be set to a first level to activate the first gate chain and inactivate the second gate chain and to a second level to inactivate the first gate chain and activate the second gate chain. The control circuit may produce the first and second control signals according to a clock signal and a general control signal for controlling the controlled delay circuit as a whole.
The control circuit may contain a frequency divider. The control circuit may divide a frequency of an input signal to the first gate chain by N (N being an integer equal to or greater than two), to produce control signals each having a period that is N times as long as a period of the input signal, supply the control signals to N sets of the first and second gate chains, and superpose outputs of the N sets, to provide an output signal having the same frequency as and a different phase from the input signal. The control circuit may halve the frequency of the input signal to the first gate chain, to produce complementary control signals each having a period twice as long as that of the input signal, supply the first control signal and second control signal to two sets of the first and second gate chains, and superpose outputs of the two sets, to provide an output signal having the same frequency as and a different phase from the input signal.
The first control signal and second control signal may be supplied to the gate circuits of the first gate chain and second gate chain through respective signal lines. The signal lines may be connected to the gate circuits of the first gate chain and second gate chain through buffers arranged for every predetermined number of the gate circuits. The buffers may be inverters through which the signal lines are alternately connected to the first and second gate chains.
Sizes of transistors forming the gate circuits of the first gate chain may be differentiate from sizes of transistors forming the gate circuits of the second gate chain, to temporally multiply the delay time generated in the first gate chain by a given value, which may correspond to a ratio of the transistor sizes, and invert the multiplied input signal. Each of the gate circuits of the first and second gate chains may be an inverter having a power source controlling transistor to be switched in response to a control signal, to activate one of the first and second gate chains.
Each of the gate circuits of the first and second gate chains may be an inverter, a level of a voltage applied to the inverters being changed to activate one of the first and second gate chains. Each common node in the first and second gate chains may be provided with a capacitor element to control signal propagation delay characteristics of the gate circuits. Capacitances of the capacitor element may be gradually increased from an input side of the first gate chain toward an output side thereof.
An output end of the first gate chain may be set to a high impedance state, an input end of the second gate chain may be fixed at first potential, an input signal of second potential supplied when the first gate chain is activated may be reversely transmitted when the second gate chain is activated, so that data of the first potential appears at an output end of the second gate chain, to thereby reproducing a time difference between a changeover point of the input signal to the first gate chain and a changeover point of the first control signal by a time difference between a changeover point of the second control signal and a changeover point of the output of the second gate chain.
An input end of the first gate chain may be provided with a one-way drive circuit for driving the first gate chain only to one of the first potential and second potential. An output end of the second gate chain may be provided with an output buffer for catching only a changeover point from first potential to second potential, or from the second potential to the first potential.
The controlled delay circuit may comprise pairs of the first and second gate chains, the first and second gate chains of each pair receiving different control signals, and a superposing output buffer for superposing outputs of the pairs of the first and second gate chains, to provide an output signal having the same frequency as and a different phase from the input signal. The outputs of the pairs of the first and second gate chains may be connected to one another through switch element each transmitting an output of first level of the corresponding pair when second gate chain of the corresponding pair is active, and the outputs of the pairs may be controlled by a common controller to a second level after a time when the superposed output of the pairs settles to the second level.
The controlled delay circuit may comprise a programmable controlled delay circuit whose delay time is programmed. The programmable controlled delay circuit may be programmed by laser after manufacturing.
According to the present invention, there is also provided a controlled delay circuit comprising a first gate chain having a plurality of first delay units connected in series of a first direction, wherein a first input signal being transferred in the first direction during a first enabled period instructed by a first control signal, and the first input signal being digitalized by a unit time-interval, and output; and a second gate chain having a plurality of second delay units connected in series of a second direction opposite to the first direction, wherein the digitalized first input signal being input to the second gate during a disable period instructed by a second control signal, and the digitalized first input signal being transferred in the second direction during a second enabled period enabled by the second control signal.
Further, according to the present invention, there is provided a timing controller comprising a first circuit having a first delay time; a second circuit having a second delay time; and a time difference expander for expanding a time difference between a changeover point of a first signal and a changeover point of a second signal xcex1 times (xcex1 being a value greater than one), to provide an output signal having a given time difference with respect to a control signal, the first signal being passed through the first circuit and the second circuit, and the second signal being passed through the first circuit.
The delay time of the second circuit may be substantially equal to the delay time of the first circuit. The first circuit may be an input buffer, and the second circuit is a delay circuit. The first signal may involve the first delay time plus the second delay time with respect to the control signal, the second signal may involve the first delay time with respect to the control signal, and the time difference may be an interval between a changeover point of the first signal and a one-cycle-behind changeover point of the second signal. The first signal may involve the first delay time plus the second delay time with respect to the control signal, the second signal may involve the first delay time with respect to the control signal and a period twice as long as that of the control signal, and the time difference may be an interval between a rise of the first signal and a fall of the second signal.
The time difference expander may double the time difference. The control signal may be a clock signal. The second circuit may comprise a first delay circuit and a second delay circuit, the first delay circuit involving a fourth delay time that is substantially equal to a third delay time of a signal transmitter for transmitting an output of the time difference expander to a circuit of the next stage, and the second delay circuit having a second delay time that is substantially equal to the first delay time. The time difference expander may expand a time difference between a changeover point of the first signal and a changeover point of the second signal N times (N being an integer equal to or greater than two), to provide an output signal that is inphase with the control signal; the first signal may be passed through the first circuit, the first delay circuit, and the second delay circuit; and the second signal may be passed through the first circuit.
The timing controller may provide an output signal before a rise or fall of the control signal and sustains the output signal for a given period around the rise or fall of the control signal.
In addition, according to the present invention, there is also provided a timing controller comprising an internal circuit, and a time difference expander for expanding a time difference between a changeover point of a first signal and a changeover point of a second signal N times (N being an integer equal to or greater than two), to provide a phase-controlled output signal, the first signal being passed through the internal circuit and produced by a cycle of a control signal, and the second signal being passed through a part of the internal circuit and produced by the next cycle of the control signal.
According to the present invention, there is provided an electric circuit comprising a clock buffer circuit, and a delay circuit for shifting a phase of an external first clock signal passing through the clock buffer circuit, wherein the delay circuit includes L (Lxe2x89xa71) groups of delay-time generation circuits for generating an appropriate phase difference suitable to the electric circuit between L groups of first control signals and L groups of second control signals; M (Mxe2x89xa71) groups of first array circuits having K (Kxe2x89xa71) number of types of unit-circuits, each type of unit-circuit being connected in series to the other type of unit-circuit in order to move data of each unit-circuit to the next unit-circuit in a first direction, and the unit-circuits of the first array circuits being enabled to start the propagations by the first control signals and being stopped by the second control signals; N (Nxe2x89xa71) groups of second array circuits having K (Kxe2x89xa71) number of types of unit-circuits, each type of unit-circuit being connected in series to the other type of unit-circuit in order to move data of each unit-circuit to the next unit-circuit in a second direction opposite to the first direction and to output the moved data through an output terminal, and the second array circuits being started when an input signal being supplied; and a data transfer circuit for transferring data from at least a part of the unit-circuit of the first array circuits to the unit-circuits of the second array circuits in order to determine data to be prefetched in the unit-circuit of the second array circuits before starting the propagations passing through the second array circuits.
The first array circuits and the second array circuits may include the same types of unit-circuits. The number of types of the unit-circuits may be one, and each of the unit-circuits may operate as an inverter circuit, when the unit-circuits are enabled by the first and second control signals. The number of types of the unit-circuits may be one, and each of the unit-circuits may operate as a driver circuit, when the unit-circuits are enabled by the first and second control signals. The number of types of the unit-circuits may be two, and one type of the unit-circuits may include a NAND gate circuit, and another type of the unit-circuits may include a NOR gate circuit.
The unit-circuits of the first array circuits may have the same configuration as that of the second array circuits, and a delay time of the first array circuits may be the same as that of the second array circuits during respective propagation period. The unit-circuits of the first array circuits and the unit-circuits of the second array circuits may be constituted by the same sizes of transistors. The unit-circuits of the first array circuits and the unit-circuits of the second array circuits may be constituted by the same layout patterns on a silicon chip.
Each of the first control signals and each of the second control signals may be transmitted through a common node, such that a propagation of the electric circuit is started when the common node is at a first level, and the propagation is stopped when the common node is at a second level. The data transfer circuit may include a data latch circuit for storing the data sent from the first array circuits. The first array circuits may include data reset circuit for initializing data of the unit-circuits of the first array circuits, before starting the propagations through the first array circuits.
The number of the unit-circuits in the first array circuits may be at least three and less than the number of the unit-circuits of the second array circuits. The electric circuit may further comprise an output synthesizing circuit for selectively outputting composite-data sent from one of the second array circuits. Each output of the second array circuits may be connected to a common output bus and a synthesizing circuit to toggle a common output bus in accordance with the outputs of the second array circuits.
The first array circuits, K (Kxe2x89xa71) number of the second array circuits, and a data transfer circuit may constitute one set of a first timing control circuit, and the data transfer circuit may transfer data from a part of the unit-circuit of the first array circuits to the unit-circuits of the second array circuits in the same set of the first timing control circuit in order to determine data to be prefetched in the unit-circuits of the second array circuits before starting the propagations passing through the second array circuits.
The electric circuit may comprise a first set of the first timing control circuit for controlling rising edges of an output signal, and a second set of the first timing control circuit for controlling falling edges of the output signal. The electric circuit may comprise a plurality sets of the first timing control circuits, and an output synthesizing circuit for outputting composite-data sent from one of the second array circuits. Each output of the sets of the first timing control circuits may be connected to a common output bus and a synthesizing circuit to toggle a common output bus in accordance with the outputs of the second array circuits. A set of the first timing control circuit may include K (Kxe2x89xa71) types of the second array circuits, each type thereof may receive a different type of data from the data transfer circuit included in the same set.
The first array circuits and the second array circuits may include the same types of unit-circuits. The number of types of the unit-circuits may be one, and each of the unit-circuits may operate as an inverter circuit, when the unit-circuits are enabled by the first and second control signals. The number of types of the unit-circuits may be one, and each of the unit-circuits may operate as a driver circuit, when the unit-circuits are enabled by the first and second control signals.
The number of types of the unit-circuits may be two, and one type of the unit-circuits may include a NAND gate circuit, and another type of the unit-circuits may include a NOR gate circuit. The unit-circuits of the first array. circuits may have the same configuration as that of the second array circuits, and a delay time of the first array circuits may be the same as that of the second array circuits during respective propagation period.
The unit-circuits of the first array circuits and the unit-circuits of the second array circuits may be constituted by the same sizes of transistors. The unit-circuits of the first array circuits and the unit-circuits of the second array circuits may be constituted by the same layout patterns on a silicon chip.
Each of the first control signals and each of the second control signals may be transmitted through a common node, such that a propagation of the electric circuit is started when the common node is at a-first level, and the propagation is stopped when the common node is at a second level. The data transfer circuit may include a data latch circuit for storing the data sent from the first array circuits. The first array circuits may include data reset circuit for initializing data of the unit-circuits of the first array circuits, before starting the propagations through the first array circuits.
The number of the unit-circuits in the first array circuits may be at least three and less than the number of the unit-circuits of the second array circuits. The first and second control signals may be generated from a first common source signal which has a first level to enable the propagation passing through the first array circuits and a second level to disable the propagation through the first array circuits.
The first level of the first common source signal may disable the propagation passing through the second array circuits, and the second level of the first common source signal may enable the propagation passing through the second array circuits. The number K of the second array circuits may be equal to a number J of the first array circuits.
The first common source signal and the input signal input into the second array circuits may be generated from a second common source signal. The electric circuit may further comprise a common-output synthesizing circuit.
Further, according to the present invention, there is also provided an electric circuit comprising a first clock buffer circuit receiving an external clock signal; a first clock delivery circuit; and a first clock timing control circuit, being supplied with an output of the first clock buffer circuit and an output of the first clock delivery circuit, for generating a preceding internal clock before the output of the first clock buffer circuit being output.
In addition, according to the present invention, there is provided an electric circuit comprising a first clock buffer circuit receiving an external clock signal; a first clock delivery circuit; a first delay circuit for duplicating delay time characteristics of the first clock buffer circuit; and a first clock timing control circuit, being supplied with an output of the first clock buffer circuit and an output of the first delay circuit, for generating a preceding internal clock before the output of the first clock buffer circuit being output.
The first delay circuit may duplicate delay time characteristics of the first clock buffer circuit and the first clock delivery circuit. The electric circuit may further comprise a first optional circuit, and the first delay circuit may duplicate delay time characteristics of the first clock buffer circuit, the first clock delivery circuit, and the first optional circuit.
The electric circuit may further comprise a first clock frequency control circuit for receiving an output of the clock buffer circuit, and an output of the first clock frequency control circuit may be also supplied to the first clock timing control circuit. The first clock timing control circuit may store capability information into a memory, and the capability information may relate to the input from the output of the first clock buffer circuit and the output of the first delay circuit.
According to the present invention, there is provided an electric circuit comprising a first clock buffer circuit receiving an external clock signal; a first clock delivery circuit; and a first clock timing control circuit, being supplied with an output of the first clock buffer circuit and an output of the first clock delivery circuit, for generating an output coincident with the external clock signal.
Further, according to the present invention, there is provided an electric circuit comprising a first clock buffer circuit receiving an external clock signal; a first clock delivery circuit; a first delay circuit for duplicating delay time characteristics of the first clock buffer circuit; and a first clock timing control circuit, being supplied with an output of the first clock buffer circuit and an output of the first delay circuit, for generating an output coincident with the external clock signal.
The first delay circuit may duplicate delay time characteristics of the first clock buffer circuit and the first clock delivery circuit. The electric circuit may further comprise a first optional circuit, and the first delay circuit may duplicate a delay time characteristics of the first clock buffer circuit, the first clock delivery circuit, and the first optional circuit. The electric circuit may further comprise a first clock frequency control circuit for receiving an output of the clock buffer circuit, an output of the first clock frequency control circuit may be also supplied to the first clock timing control circuit, and the first clock timing control circuit may generate an output coincident with a part of the external clock signal. The first clock timing control circuit may store capability information into a memory, the capability information may relate to the input from the output of the first clock buffer circuit and the output of the first delay circuit, and the first clock timing control circuit may generate an output coincident with a part of the external clock signal.
In addition, according to the present invention, there is provided an electric circuit comprising a delay circuit for changing a phase of an external first clock signal, to form a second clock signal, an optional circuit, and a buffer for providing an output according to an output of the optional circuit in synchronization with the second clock signal, wherein the delay circuit comprises a first gate chain for measuring a time difference between a changeover point of a first control signal and a changeover point of a second control signal; and a second gate chain, receiving a third control signal which is generated in the first circuit and represents the time difference, for providing an appropriate delay time from an input to an output depending on the time difference.
The third control signal may be stored in a memory or a register circuit to fix the third control signal. The data stored in the memory or register circuit may be renewed in accordance with specific clock cycles.
Further, according to the present invention, there is also provided an electric circuit comprising a delay circuit for changing a phase of an external first clock signal, to form a second clock signal, an optional circuit, and a buffer for providing an output according to an output of the optional circuit in synchronization with the second clock signal, wherein the delay circuit comprises a first gate chain having gate circuits connected in series to transmit a signal in a first direction; a second gate chain having gate circuits connected in series to transmit a signal in a second direction opposite to the first direction; and a control circuit for activating and inactivating at least a part of the first gate chain according to a first control signal and at least a part of the second gate chain according to a second control signal, and at least one node in the first gate chain being short-circuited to at least one node in the second gate chain, to invert an input signal to the first gate chain and provide an output signal from the second gate chain.
According to the present invention, there is provided a controlled delay circuit comprising a first converter circuit for converting a first time difference between a changeover point of a first input signal and a changeover point of a second input signal into first gate step information indicating the number of gates corresponding to the first time difference, and a second converter circuit for converting second gate step information indicating the number of gates determined according to the first gate step information into a second time difference, to delay a third input signal supplied to the second converter circuit by the second time difference and provide the delayed signal as an output signal; and the first converter circuit having an array of at least one first unit circuits regularly arranged to transmit the first input signal in a first direction; the second converter circuit having an array of at least one second unit circuits regularly arranged to transmit the third input signal in a second direction opposite to the first direction, the second unit circuit reproducing the delay time of the first unit circuit.
The first gate step information may be a set of data gathered from all or part of the first unit circuits, and the second gate step information may be a set of data supplied to all or part of the second unit circuits. Signals may synchronous to the bits of the first gate step information, respectively, may be supplied as the second gate step information directly to the second converter circuit. Signals that are in phase with the bits of the first gate step information may be supplied as the second gate step information directly to the second converter circuit. Signals that are opposite phase to the bits of the first gate step information may be supplied as the second gate step information directly to the second converter circuit.
The controlled delay circuit may further comprise a gate step information converter circuit disposed between the first converter circuit and the second converter circuit, for converting the first gate step information into the second gate step information. The gate step information converter circuit may directly supply data from the first unit circuits to the second unit circuits, respectively, to adjust the delay time of the second converter circuit to that of the first converter circuit.
The gate step information converter circuit may supply data from every xe2x80x9cMxe2x80x9dth of the first unit circuits to the second unit circuits, to set the delay time of the second converter circuit to 1/M of that of the first converter circuit. Data from every xe2x80x9cMxe2x80x9dth of the first unit circuits may be supplied to the second unit circuits through a required number of inverters. The gate step information converter circuit may supply data from one of the first unit circuits to M pieces of the second unit circuits, to set the delay time of the second converter circuit to M times as long as that of the first converter circuit.
The controlled delay circuit may further comprise a reset portion where input and output signals to and from the second unit circuits may be reset just before the third input signal is supplied to the second converter circuit. The controlled delay circuit may further comprise latch circuits provided for the first unit circuits, respectively, for storing data from the first unit circuits, respectively. The controlled delay circuit may further comprise latch circuits provided for the second unit circuits, respectively, for storing data to the second unit circuits, respectively.
The unit circuits may have inverting gate circuits at least having an inversion function, the delay time of each gate of the inverting gate circuits being used as a unit time for conversion. A period between a changeover point of the first input signal and a changeover point where the second input signal changes from a first level to a second level may be held as the first gate step information corresponding to the first time difference. Even ones of the unit circuits may be NAND gate circuits and odd ones thereof are NOR gate circuits. The first and second unit circuits may bias input thresholds of the first and second converter circuits, to hasten the delay time of those of the unit circuits that transmit signals dependent on the first input signal.
Even ones of the unit circuits may be NOR gate circuits and odd ones thereof are NAND gate circuits. The first and second unit circuits may bias input thresholds of the first and second converter circuits, to hasten the delay time of those of the unit circuits that transmit signals dependent on the first input signal. The unit circuits may have reset-signal input terminals to set outputs opposite to expected values just before the signals dependent on the first input signal are transmitted.
The unit circuits may have data fetch circuits for fetching data from the unit circuits at a changeover point of the second input signal. The unit circuits may have delay time adjusting capacitors each having capacitance corresponding to an input capacitance of the data fetch circuit, for equalizing the delay time of each of the unit circuits to that of one unit circuit of the first converter circuit. The second unit circuits may have reset-signal input terminals to set outputs opposite to expected values just before signals dependent on the third input signal are transmitted.
The controlled delay circuit may comprise two first converter circuits to separately set a delay time of a rise of the first input signal and a delay time of a fall of the first input signal in the first converter circuit. Even and odd unit circuits in the first converter circuits may be alternately NAND and NOR unit circuits, and even unit circuits for producing a delay time of a rise of a signal and odd unit circuits for producing a delay time of a fall of the signal in the second converter circuit may be alternately NAND and NOR unit circuits with the arrangement of the NAND and NOR unit circuits for the rise delay time being opposite to that of the NAND and NOR unit circuits for the fall delay time.
The controlled delay circuit may comprise a plurality of second converter circuits to separately provide pieces of delay time for a rise and fall of the second input signal, to change the oscillation frequency of the third input signal. The controlled delay circuit may comprise a plurality of second converter circuits to separately provide pieces of delay time for a rise and fall of the second input signal, to increase the oscillation frequency of the third input signal by a multiple.
A first converter circuit may convert a time difference between a rise of the first input signal and a changeover point of the second input signal into gate step information indicating the number of gates, another first converter circuit may convert a time difference between a fall of the first input signal and a changeover point of the second input signal into gate step information indicating the number of gates, and a delay time of a rise of the third input signal supplied to the second converter circuit and a delay time of a fall of the third input signal may be separately determined according to the two pieces of gate step information. A first converter circuit may convert a time difference between a rise of the first input signal and a changeover point of the second input signal into gate step information indicating the number of gates, and another first converter circuit may convert a time difference between a fall of the first input signal and a changeover point of the second input signal into gate step information indicating the number of gates, to separately provide pieces of delay time for a rise and fall of the second input signal with respect to the second converter circuit according to the two pieces of gate step information and change the oscillation frequency of the third input signal.
The first input signal may be supplied to the first one of the first unit circuits. The first input signal may be supplied as a reset signal to the first unit circuits, to put a delay forming gate in each of the first unit circuits in a reset state or an inverted state. An input to the first one of the first unit circuits may be set to a fixed level, and when the first input signal specifies the inverted state, the first converter circuit may start signal transmission. The controlled delay circuit may comprise a plurality of second converter circuits, the first one of the unit circuits in at least one of the second converter circuits may include a NAND delay circuit, the first one of the unit circuits in at least one of the second converter circuits including a NOR delay circuit, and an input level to the first one of the unit circuits may be fixed to form an inverter delay circuit. Only the first one of the second unit circuits may include an inverter delay circuit.
The first one of the second unit circuits may clamp an input to invert the second gate step information if the time difference is longer than the delay time of the first converter circuit. The first one of the second unit circuits may clamp an input so that the delay circuit in the first one of the second unit circuits serves as an inverter.
The first and second input signals may be periodically supplied to the first converter circuit at intervals of M changeover points, to reproduce the second gate step information. The reproduced second gate step information may be reset when the second converter circuit does not transmit the third input signal. A change between new and old values of the second-gate step information may be set below a given value, to gradually change the delay time. The controlled delay circuit may comprise two second converter circuits to separately form delays for a rise and fall of an input signal, an output in each of the second converter circuits being connected to a synthesized output node through a bus, and an output section in each of the second converter circuits being provided with a circuit for providing given data within a predetermined period after an output is changed from one to another, to sufficiently increase output impedance in the remaining period.
The controlled delay circuit may comprise a plurality of pairs of second converter circuits, one of the second converter circuits of each pair delaying the timing of a rise of an output, the other of the second converter circuits of each pair delaying the timing of a fall of the output, the output changeover timing of opposite output being determined by another output changeover timing means, an output in each of the second converter circuits and the output of the output changeover timing means being connected to a synthesis output node through buses. The controlled delay circuit may comprise 2M second converter circuits, to provide an output signal whose frequency is M times as large as that of the third input signal. Each of the second converter circuits may be provided with a delay time fine adjustment circuit, so that each of the second converter circuits may provide an output signal whose timing frequency is synchronous to the third input signal.
The second converter circuit may have a delay circuit for electrically controlling the delay time of the second converter circuit. The controlled delay circuit may comprise an odd number of second converter circuits, the inputs and outputs of the second converter circuits are connected to one another to form a ring oscillator to provide a signal whose period is L/M times (L and M being integers) the time difference set by the first converter circuit.
The controlled delay circuit may comprise an even number of second converter circuits and an odd number of inverter gates, the inputs and outputs of the second converter circuits may be connected to one another through inverter gates, to form a ring oscillator to provide a signal whose period is L/M times (L and M being integers) the time difference set by the first converter circuit. The second converter circuits may have delay circuits for electrically controlling a delay time, the delay circuits may be controlled to synchronize the changeover timing of the output of any one of the second converter circuits with the changeover timing of an external clock signal, to provide a signal whose period is L/M times (L and M being integers) the time difference set by the first converter circuit. The second converter circuits may comprise delay circuits having a fixed delay time that is determined in consideration of manufacturing fluctuations, the delay circuits may be controlled to synchronize the changeover timing of the output of any one of the second converter circuits with the changeover timing of an external clock signal, to provide an internal clock signal that changes more quickly than the external clock signal by the fixed time.
According to the present invention, there is provided a controlled delay circuit for adding a given delay to an input signal and providing a delayed output signal, comprising a gate array having cascaded gate units to provide the output signal; and a gate specifying circuit for specifying, according to stored data, one of the gate units to start delaying the input signal.
Each of the gate units may receive the output of the preceding gate unit, the input signal, and the output of a corresponding unit circuit of the gate specifying circuit. The controlled delay circuit may further comprise an input switching circuit for supplying the input signal to one of the gate units according to data stored in the gate specifying circuit. Each of the gate units may receive the output of the preceding gate unit and the output of a corresponding switching unit of the switching circuit. Each of the switching units may be switched according to the output of a corresponding unit circuit of the gate specifying circuit.
The gate specifying circuit may be a register circuit that receives a write signal and an address signal to specify one of the gate units that starts to delay the input signal. The register circuit may be reset in response to a reset signal.
The gate specifying circuit may be a shift register circuit that receives a shift signal to specify one of the gate units that starts to delay the input signal. The shift register circuit may be reset in response to a reset signal.
The controlled delay circuit may further comprise a comparator for comparing the output signal of the gate array with a reference signal; and a controller for feed-back controlling, in response to the output of the comparator, signals supplied to the gate specifying circuit to specify one of the gate units that starts to delay the input signal.
Further, according to the present invention, there is also provided a control signal generator for generating a control signal whose period is determined according to the period of an input signal, comprising a first gate array having cascaded gate units to receive the input signal; a second gate array having cascaded gate units to receive the output of the first gate array; a comparator for comparing the output of the second gate array with the input signal; and a gate specifying circuit for specifying, according to the output of the comparator, one of the first gate units that starts to delay the input signal as well as one of the second gate units that starts to delay the output of the first gate array.
The control signal generator may provide an output signal whose frequency is twice as large as that of the input signal. The control signal generator may further comprise an output logic circuit for providing a result of logical operation of the output of the first gate array and the output of the second gate array. The control signal generator may further comprise an output logic circuit for providing a result of logical operation of the input signal and the output of the first gate array.